Our German client, a leading worldwide supplier of high performance semiconductor sensor solutions is in search of a:

Responsibilities

• From project start define DFT strategy in analog (primarily) and digital domain
• Interact with test engineers, technical leads and designers to identify limitations of test hardware: design and find optimum DFT and ASIC observability solutions
• Evaluate possible failure modes and define test modes to debug and mitigate failure modes
• Define all test modes that can allow extended testing of the ASIC
• Implement and verify DFT schemes
• Perform test coverage analysis
• Define DFT cook-book to all designers with best DFT guidelines

Qualifications

• Master’s degree in Electrical / Computer Engineering with 10 years  of experience in Design for Test, or a Bachelor’s degree with 15 years of experience
• Excellent failure mode analysis skills
• Experience on ATE and debug
• Knowledge of analog and mixed signal design
• Knowledge of ATPG, scan insertion, coverage improvement, BIST and related simulations.
• Collaborative and respectful team player, passionate about achieving team goals
• Excellent communication skills (both oral and written) are required
• Experience with relevant CAD tools