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Senior/Staff Design Verification Engineer

Job Title
Senior/Staff Design Verification Engineer
Job ID
27736397
Location
Austin, TX,  
Other Location
Campbell, CA
Description
Senior/Staff Design Verification Engineer
Leading SoC IP Firm
Full Time Role
Austin, TX or Bay Area, CA (Hybrid)


Benefits You’ll Love: 
  • Medical, Dental, and Vision
  • Life Insurance
  • Disability
  • 401k Matching
Become a key player as a Design Verification Engineer:
Nextdeavor is seeking a candidate to join our expert team in designing and delivering interconnect and memory hierarchy solutions for advanced mobile, telecom, automotive, and consumer SoC designs. You'll utilize a powerful language combining traditional RTL with cutting-edge software to create highly configurable, testable, and high-quality solutions. Discover the diverse applications of your work every day.

​​​​​Join a successful startup where you can influence the development environment, architecture, and verification processes. Collaborate with experienced industry experts who are passionate about their work.

Here’s how you’ll make an impact on the team:
  • Develop and debug advanced UVM-based test benches.
  • Define, document, develop, and execute RTL verification tests and coverage at the system level.
  • Conduct performance and power-aware verification.
  • Triage regressions and debug RTL designs using Verilog and SystemVerilog.
  • Improve and refine verification processes, methodologies, and metrics.
  • Apply UVM expertise to complex SoC projects, from test bench development to verification closure.
Here’s what you’ll need to be successful in this role:
  • Bachelor's of Science degree in EE, CS, or equivalent experience, MS Degree preferred
  • 10+ years of design and verification experience, with a preference for interconnect verification experience
  • Expertise in enhancing verification flows using scripting languages such as Shell scripts, Python, and JavaScript
  • Strong skills in debugging RTL (Verilog) and UVM/C test benches
  • Experience integrating vendor-provided VIPs for unit and system-level verification
  • Familiarity with Arm AMBA protocols
  • Experience with high-performance, low-power designs on highly visible projects
​​​​Pay Range:
$150,000 - $200,000 annually

Ready to make your mark? Take the leap and apply directly here: https://j.brt.mv/jb.do?reqGK=27736397&refresh=true – your application is in good hands.​​​​​​
Pay Range
$150,000.00   Annually to $200,000.00   Annually

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