As a Logic Design, Intern with ForwardEdge ASIC, you will be developing ASIC and FPGA designs that will be included in an array of complex, innovative and exciting products.    Your responsibility will be developing RTL for both ASIC and FPGA design environments.   You will benefit from the experience of highly qualified digital design engineers on the team.   You will work closely with verification, analog design, physical design, and architecture teams.

Responsibilities include, but are not limited to the following:

• • Working under the direction of experienced engineers/architects to understand the function and requirements for entry-level design blocks.
  • Writing detailed implementation plans and specifications for design blocks. 
  • Writing Register Transfer Level (RTL) code using industry standard hardware description languages.
  • Writing lower-level test bench code to verify baseline functionality and features for design blocks.
  • Writing test plans and coordinating with the Design Verification team to fully verify design blocks.
  • Synthesizing RTL code using industry standard tools and analyzing results. 
  • Providing RTL updates to meet Power, Performance and Area (PPA) or Size, Weight and Power (SwaP) requirements. 
  • Writing and executing plans for the post silicon lab validation.    

Qualified Applicants will have the following education and experience:

• Actively working toward a bachelor’s or master’s degree in electrical engineering or computer engineering.
• Strong course work in VLSI design, digital logic
• Proficiency or intermediate level Programming skills such as Python

Location and duration:

• Onsite in St. Paul, Minnesota for 12 weeks in the summer of 2026.