As an ASIC Design Verification Engineer Intern with ForwardEdge ASIC, you will be verifying ASIC and FPGA designs that will be included in an array of complex, innovative and exciting products.    Your responsibility will include all aspects of ASIC verification.   You will benefit from the experience of a highly qualified ASIC team.

Responsibilities include, but are not limited to the following:

• Working under the direction of experienced verification engineers to understand how to verify the functions and requirements for design blocks.
• Creating verification environments utilizing industry standard verification languages including, but not limited to SystemVerilog.
• Understanding block-to-top UVM constrained random environments.
• Utilizing best practices methodology for functional coverage, assertions, debug and formal verification.
• Working closely with the digital design engineers to ensure comprehensive functional and code coverage metrics.  
• Process and methodology automation utilizing common scripting languages (i.e. python, perl, tcl).  

Qualified Applicants will have the following education and experience:

• Actively working toward a bachelor’s or master’s degree in electrical engineering or computer engineering.
• Strong course work in VLSI design, digital logic
• Proficiency or intermediate level Programming skills such as Python or other object-oriented languages

Location and duration:

• Onsite in St. Paul, Minnesota for 12 weeks in the summer of 2026.