Summary: ForwardEdge ASIC is seeking a highly skilled ASIC Design Verification Engineer to lead our verification efforts across complex ASIC and FPGA designs. In this role, you will be responsible for driving the verification strategy, methodologies, and implementation from inception to delivery. Your expertise will be crucial in ensuring that our ASIC designs meet functional and performance requirements while adhering to high standards of quality and reliability.

Key Responsibilities:

• Lead the verification efforts in planning, developing, and executing verification strategies for ASIC and FPGA designs.
• Define verification methodologies, verification plans, and environments to ensure comprehensive verification coverage.
• Collaborate closely with architects, design, and analog teams to understand design specifications and develop efficient verification strategies.
• Drive the development of verification components, including test benches, test cases, and assertion-based verification IP.
• Conduct complex debugging and root cause analysis of verification failures to ensure timely resolution.
• Mentor and guide junior verification engineers, providing technical leadership and fostering a culture of innovation and excellence.
• Stay updated with industry trends, tools, and methodologies in verification to continually improve our capabilities.

Qualifications:

• Bachelor's degree in computer engineering, electrical engineering, or related field
• 10+ years of relevant prior experience working as an ASIC Design Verification Engineer.
• Hands-on experience in developing verification environments and test benches for complex ASIC and FPGA designs.
• Strong leadership skills with experience in leading or mentoring verification engineers.
• Clearance: This position requires a US government security clearance. As such, US citizenship is required.

Nice to Have:

• Experience in verification of high-speed interfaces (e.g., PCIe, DDR, UCIe), AI/ML, complex data processing, and/or processor-based designs.
• Familiarity with formal verification techniques and tools.
• Experience with verification of ASICs targeting AI/ML, networking, or automotive applications.

·         Master’s degree in computer engineering, electrical engineering, or a related field.

Work Environment: The work environment for this role typically involves a combination of office-based activities and collaboration with logic design, analog design, CAD, and physical verification teams. Occasional travel may be required for project meetings or customer engagements.

Benefits:

·         Work-life balance: Flexible 9/80 Work schedules with every other Friday off, hybrid work with primary location being in St. Paul, MN

·         Competitive benefit package: Including options for healthcare and medical coverage, 401K Retirement Benefits with company contribution, as well as a generous holidays and PTO allotment. Selected candidate may also be eligible for short-term and long-term incentives.

Please note: the compensation range listed above is a good-faith estimate for this role. Actual pay will be based on an individual’s experience, skills, qualifications, and other job-related factors.